Designing the bias circuit for a Field-Effect Transistor (FET) is crucial to ensure stable and reliable operation in analog amplifier circuits. The purpose of a bias circuit is to establish a proper quiescent operating point (Q-point), enabling the FET to operate in the saturation region (constant-current region) for undistorted signal amplification. Common FET types include MOSFETs and JFETs, and while their biasing methods differ slightly, the core objective remains the same: to stabilize the gate-to-source voltage (VGS) and maintain a constant drain current (ID).
1. Self-Bias Circuit (Suitable for JFETs and Depletion-Mode MOSFETs)
Self-bias is the simplest FET biasing method, commonly used in JFET amplifiers. The circuit consists of a source resistor (RS) and a gate-grounding resistor (RG). The drain current ID flows through RS, creating a voltage drop VS = ID × RS. Since the gate is grounded via RG, VG = 0, and thus VGS = -VS = -ID × RS. This negative feedback mechanism automatically stabilizes ID: if ID increases, VS rises, making VGS more negative, which in turn reduces ID, achieving self-regulation.
Design steps:
Determine the desired ID and VGS (refer to the device’s transfer characteristic curve).
Calculate RS = |VGS| / ID.
Select RG (typically 1MΩ to 10MΩ) to provide high input impedance without affecting biasing.
2. Voltage-Divider Bias Circuit (Suitable for Enhancement-Mode MOSFETs)
Enhancement-mode MOSFETs require a positive VGS to turn on, so a voltage divider (R1, R2) is commonly used to supply a positive gate voltage. The source still connects to RS, forming negative feedback. VGS = VG - VS, where VG = VDD × R2 / (R1 + R2). When ID increases, VS rises, reducing VGS and suppressing further increase in ID, thereby enhancing stability.
Key design considerations:
Select RS based on required ID and VGS.
Set VG > VTH (threshold voltage) to ensure conduction.
R1 and R2 should be much smaller than RG to stabilize VG, while avoiding excessive power consumption.
3. Drain-Feedback Bias
This method feeds the drain voltage back to the gate through a resistor, using VDS to indirectly influence VGS and stabilize the operating point. It is simple but less stable than the voltage-divider method.
Design Considerations
Temperature Stability: ID increases with temperature; RS provides negative feedback for compensation.
Input Impedance: RG should be large enough to preserve the FET’s high input impedance advantage.
Supply Voltage: Ensure VDS is sufficiently large to keep the FET in saturation (VDS > VGS - VTH).
A well-designed bias circuit ensures high linearity and low distortion in FET amplifiers, forming the foundation of analog circuit design.
